The increasing demand for information capacity of CMOS components requires a continuously higher packing density and higher speed in the circuits and thus a shrinking of the line-widths, distances and layer thicknesses.
The shrinking line width also calls for lower supply voltages and signal voltages. For digital components this is a benefit since it saves electrical power, while noise margins are relatively large. However, in analog high frequency circuits noise margins are a concern. Modern, low voltage CMOS processes cannot withstand the voltage levels needed to preserve signal-to-noise ratios in high performance analog circuits.
Lateral DMOS structures have previously been used in for example RF power amplifiers, by combining high breakdown voltage with good high frequency performance. In these structures, the channel area has been diffused from the edge of e.g. the gate structure. Such a provision needs an additional annealing step, which may not be compatible with a standard CMOS process flow since the thermal budget in many processes is very limited. Furthermore, an optimal doping gradient in the channel area is not obtained since the highest channel doping is automatically obtained closest to the source area.
The breakdown voltage of the MOS transistor can be increased by means of the so-called extended drain technique. For an NMOS transistor, the active area is defined in a p-well region. In this region, an n-area is formed to define an extended drain area that may be depleted when the drain voltage is increased.
A further improvement may be achieved by employing a buried N-type layer that has the function of isolating the active p-well region of the transistor from the substrate. This has earlier been incorporated using epitaxy together with the extended drain technique in the isolated RESURF LDMOS (REduced SURface Field Lateral Double-diffused MOS) transistor for so-called “high side driver” applications as disclosed in U.S. Pat. No. 5,286,995.